1. Field of the Invention
The present invention relates to a flip-flop. In particular, the present invention relates to a hybrid latch flip-flop.
2. Prior Art
The TFT-LCD is now gradually becoming a standard output apparatus for various digital products. However, the TFT-LCD still needs a proper driving circuit to let it work stably.
In general, the driving circuit of a TFT-LCD can be divided into two parts, one is the source driving circuit and the other is the gate driving circuit. The source electrode in the TFT-LCD is used for controlling the gray level of each pixel unit of the TFT. The gate electrode driving circuit is used for controlling the scanning of each pixel unit. These two kinds of driving circuits both apply shift registers as core circuit units. Latch units and flip-flops are the common choice for use as the shift registers. There are many kinds of flip-flops, such as the SR flip-flop, the JK flip-flop, the D flip-flop, and the T flip-flop. In these kinds of flip-flops, the D flip-flop is commonly used as the shift register. That is to say, the D flip-flop is always used as the core circuit unit in the TFT-LCD driving circuit.
However, the D flip-flop according to the prior art still has many disadvantages. It has a long transition period and easily shifts the clock period. For this reason, people skilled in the art have developed a hybrid latch flip-flop for solving the above problems.
Referring to FIG. 11, a hybrid latch flip-flop is disclosed by H. Partovi, R. Burd, U. Salim, F. Webber, L. DiGregorio, and D. Draper in “Flow-through latch and edge-triggered flip-flop hybrid elements”, published in ISSCC Dig. Tech. Papers, February 1996, pp. 138–139. The hybrid latch flip-flop 100 according to the prior art comprises a clock input 101, an inverter unit 110, a latch flip-flop 130, a buffer unit 150, a data input 103, and a data output 105. The latch flip-flop 130 comprises a data sample unit 140 and a data hold unit 149.
The inverter unit 110 comprises a first inverter 111, a second inverter 112, and a third inverter 113. The input of the first inverter 111 is connected to the clock input 101. The output of the first inverter 111 is connected to the input of the second inverter 112. The output of the second inverter 112 is connected to the input of the third inverter 113. The output of the third inverter 113 is connected to the latch flip-flop 130.
The data sample unit 140 comprises four PMOS type transistors and six NMOS type transistors. The four PMOS type transistors comprise a first PMOS type transistor 131, a second PMOS type transistor 132, a third PMOS type transistor 133, and a fourth PMOS type transistor 134. The six NMOS type transistors comprise a first NMOS type transistor 141, a second NMOS type transistor 142, a third NMOS type transistor 143, a fourth NMOS type transistor 144, a fifth NMOS type transistor 145, and a sixth NMOS type transistor 146. The sources of the four PMOS type transistors are connected to a power source 104. The gate of the first PMOS type transistor 131, the gate of the first NMOS type transistor 141, and the gate of the fourth NMOS type transistor 144 all are connected to the clock input 101. The gate of the second PMOS type transistor 132 and the gate of the second NMOS type transistor 142 all are connected to the data input 103. The output of the third inverter 113 is connected to the gate of the third NMOS type transistor 143, the gate of the sixth NMOS type transistor 146, and the gate of the third PMOS type transistor 133. The drain of the first PMOS type transistor 131 is connected to the drain of the first NMOS type transistor 141, the drain of the second PMOS type transistor 132, the drain of the third PMOS type transistor 133, the gate of the fourth PMOS type transistor 134, and the gate of the fifth NMOS type transistor 145. The source of the first NMOS type transistor 141 is connected to the drain of the second NMOS type transistor 142. The source of the second NMOS type transistor 142 is connected to the drain of the third NMOS type transistor 143. The drain of the fourth PMOS type transistor 134 is connected to the drain of the fourth NMOS type transistor 144. The source of the fourth NMOS type transistor 144 is connected to the drain of the fifth NMOS type transistor 145. The source of the fifth NMOS type transistor 145 is connected to the drain of the sixth NMOS type transistor 146. The source of the third NMOS type transistor 143 and the source of the sixth NMOS type transistor are connected to ground (0 volts).
The data hold unit 149 comprises a fourth inverter 147 and a fifth inverter 148. The input of the fourth inverter 147 and the output of the fifth inverter 148 are connected to the drain of the fourth PMOS type transistor 134. The output of the fourth inverter 147 and the input of the fifth inverter 148 are connected to the buffer unit 150.
The buffer unit 150 comprises a sixth inverter 151. The input of the sixth inverter 151 is connected to the output of the fourth inverter 147. The output of the sixth inverter 151 is connected to the data output 105.
The clock signal is inputted from the clock input 101. When the clock signal is at low level, the first NMOS type transistor 141 and the fourth NMOS type transistor 144 are placed in a non-conducting state, and the first PMOS type transistor 131 is placed in a conducting state. The three inverters in the inverter unit 110 transform the clock signal from low level to high level. The high level signal places the third NMOS type transistor 143 and the sixth NMOS type transistor 146 in a conducting state, and places the third PMOS type transistor 133 in a non-conducting state. The node V1 shown in FIG. 11 would be charged to high voltage, VDD(whose level is equivalent to the power source 104). The high voltage places the fourth PMOS type transistor 134 in a non-conducting state, and keeps the voltage value of the data output 105.
When the positive edge of the clock signal arrives, the first NMOS type transistor 141 and the fourth NMOS type transistor 144 are placed in a conducting state. The third NMOS type transistor 143 and the sixth NMOS type transistor 146 remain in the conducting state in a delay period which is determined by a delay time of the inverter unit 110. If the data signal from the data input 103 is at low level, the second PMOS type transistor 132 is placed in a conducting state, the node V1 is charged to high voltage, the fifth NMOS type transistor 145 is in a conducting state, and the fourth PMOS type transistor 134 is in a non-conducting state. The source of the fourth PMOS type transistor 134 is connected to ground through the fourth, fifth, and sixth NMOS type transistors 144, 145, 146. On the other hand, if the data signal from the data input 103 goes high, the second NMOS type transistor 142 is placed in a conducting state, the second PMOS type transistor 132 is in a non-conducting state, and the node V1 is connected to ground through the fourth, fifth, and sixth NMOS type transistors 144, 145, 146. Because the node V1 is at low level, the fourth PMOS type transistor 134 is placed in a conducting state, and the fifth NMOS type transistor 145 is in a non-conducting state. The drain of the fourth PMOS type transistor 134 outputs the high voltage to the data hold unit 149. In this period, the latch flip-flop is viewed as placed in a conducting state, and then the data signal from data input can be sampled and hold. Once the node CKDB shown in FIG. 11 turns to low level, the connection between the node V1 and data input is weaker and the latch flip-flop 130 is viewed as in a non-conducting state. After the negative edge of the clock signal arrives, the first PMOS type transistor 131 remains in a conducting state and the node V1 is held at high voltage VDD. The data signal from the data input 103 cannot be sampled.
Referring to FIG. 12, this is a sequence diagram of the hybrid latch flip-flop of FIG. 11. V(D), V(Clock), and V(Q) shown in FIG. 12 respectively represent the waveform diagram of the data input 103, the clock input 101, and the data output 105 of FIG. 11. As shown in FIG. 12, the data output 105 is at low level before Tn. When the positive edge of the clock signal arrives at Tn, the data input 103 is at high level, and this high level would be sampled and output to make the data output 105 change from low to high. Before Tn+1, the data input 103 is at low level, and the data output 105 is at high level. At Tn+1, the data input 103 remains at low level, and this low level is sampled and output to make the data output 105 change from high to low. Before Tn+2, the data input 103 is at low level, and the data output is at low level too. At Tn+2, the low level of the data input 103 is sampled and the data output 105 remains at low level. Before Tn+3, the data input 103 is at high level and the data output 105 is at low level. At Tn+3, the high level of the data input 103 is sampled and the data output 105 changes from low to high. Before Tn+4, the data input 103 is at high level and the data output is at high level, too. At Tn+4, the high level of the data input 103 is sampled and the data output 105 remains at high level. Before Tn+5, the data input 103 is at low level and the data output 105 is at high level. At Tn+5, the low level of the data input 103 is sampled and the data output 105 changes from high to low.
When applying the hybrid latch flip-flop of the prior art to the driver circuit of the LCD, each column electrode and row electrode needs an exclusive hybrid latch flip-flop (HLFF) 100. However, the HLFF 100 comprises too many transistors and causes high power consumption in the driver circuit. In order to meet the requirement of low power consumption of the driver circuit, the HLFF applied in the LCD must have lower power consumption. On the other hand, a new HLFF design having the same function but lower power consumption is demanded.
According to the above description, to provide a new HLFF having lower power consumption is necessary.